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HY29F400A
4 Megabit (512Kx8/256Kx16) 5 Volt-only Flash Memory
KEY FEATURES 5 Volt Read, Program, and Erase - Minimizes system-level power requirements High Performance - Access times as fast as 50 ns Low Power Consumption - 20 mA typical active read current in byte mode, 28 mA typical in word mode - 30 mA typical program/erase current - 5 A maximum CMOS standby current Compatible with JEDEC Standards - Package, pinout and command-set compatible with the single-supply Flash device standard - Provides superior inadvertent write protection Sector Erase Architecture - Boot sector architecture with top and bottom boot block options available - One 16 Kbyte, two 8 Kbyte, one 32 Kbyte and seven 64 Kbyte sectors in byte mode - One 8 Kword, two 4 Kword, one 16 Kword and seven 32 Kword sectors in word mode - A command can erase any combination of sectors - Supports full chip erase Erase Suspend/Resume - Temporarily suspends a sector erase operation to allow data to be read from, or programmed into, any sector not being erased GENERAL DESCRIPTION The HY29F400A is a 4 Megabit, 5 volt only CMOS Flash memory organized as 524,288 (512K) bytes or 262,144 (256K) words. The device is offered in industry-standard 44-pin PSOP and 48-pin TSOP packages. The HY29F400A can be programmed and erased in-system with a single 5-volt VCC supply. Internally generated and regulated voltages are provided for program and erase operations, so that the device does not require a high voltage power supply to perform those functions. The device can also be programmed in standard EPROM programmers. Access times as fast as 55 ns over the full operating voltage range of 5.0 volts 10% are offered for timing compatibility with the zero wait state requirements of high speed microprocessors. A 55 ns version operating over 5.0 volts 5% is also
Preliminary Revision 1.0, January 2002
Sector Protection - Any combination of sectors may be locked to prevent program or erase operations within those sectors Temporary Sector Unprotect - Allows changes in locked sectors (requires high voltage on RESET# pin) Internal Erase Algorithm - Automatically erases a sector, any combination of sectors, or the entire chip Internal Programming Algorithm - Automatically programs and verifies data at a specified address Fast Program and Erase Times - Byte programming time: 7 s typical - Sector erase time: 1.0 sec typical - Chip erase time: 11 sec typical Data# Polling and Toggle Status Bits - Provide software confirmation of completion of program or erase operations Ready/Busy# Output (RY/BY#) - Provides hardware confirmation of completion of program and erase operations 100,000 Program/Erase Cycles Minimum Space Efficient Packaging - Available in industry-standard 44-pin PSOP and 48-pin TSOP and reverse TSOP packages LOGIC DIAGRAM
18 A[17:0] DQ[7:0] 7 CE# OE# WE# RESET# BYTE# RY/BY# DQ[14:8] DQ[15]/A-1 8
HY29F400A
available. To eliminate bus contention, the HY29F400A has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device is compatible with the JEDEC single power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings, from where they are routed to an internal state-machine that controls the erase and programming circuits. Device programming is performed a byte or word at a time by executing the four-cycle Program command. This initiates an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The HY29F400A's sector erase architecture allows any number of array sectors to be erased and reprogrammed without affecting the data contents of other sectors. Device erasure is initiated by executing the Erase command. This initiates an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase cycles, the device automatically times the erase pulse widths and verifies proper cell margin. To protect data in the device from accidental or unauthorized attempts to program or erase the device while it is in the system (e.g., by a virus), the device has a Sector Protect function which BLOCK DIAGRAM hardware write protects selected sectors. The sector protect and unprotect features can be enabled in a PROM programmer. Temporary Sector Unprotect, which requires a high voltage, allows in-system erasure and code changes in previously protected sectors. Erase Suspend enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The device is fully erased when shipped from the factory. Addresses and data needed for the programming and erase operations are internally latched during write cycles, and the host system can detect completion of a program or erase operation by observing the RY/BY# pin, or by reading the DQ[7] (Data# Polling) and DQ[6] (Toggle) status bits. Reading data from the device is similar to reading from SRAM or EPROM devices. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The host can place the device into the standby mode. Power consumption is greatly reduced in this mode.
DQ[15:0]
A[17:0], A-1
STATE CONTROL
DQ[15:0] WE# CE# OE# BYTE# RESET# RY/BY# PROGRAM VOLTAGE GENERATOR COMMAND REGISTER
ERASE VOLTAGE GENERATOR AND SECTOR SWITCHES I/O CONTROL
I/O BUFFERS
DATA LATCH
VCC DETECTOR
TIMER
A[17:0], A-1
ADDRESS LATCH
Y-DECODER
Y-GATING
X-DECODER
4 Mb FLASH MEMORY ARRAY
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HY29F400A
PIN CONFIGURATIONS
NC RY/BY# A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# VSS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 RESET# WE# A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
PSOP44
Standard TSOP48
A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Reverse TSOP48
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE# RESET# NC NC RY/BY# NC A17 A7 A6 A5 A4 A3 A2 A1
CONVENTIONS Unless otherwise noted, a positive logic (active High) convention is assumed throughout this document, whereby the presence at a pin of a higher, more positive voltage (nominally 5VDC) causes assertion of the signal. A `#' symbol following the signal name, e.g., RESET#, indicates that the signal is asserted in a Low state (nominally 0 volts).
Whenever a signal is separated into numbered bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of bits may also be shown collectively, e.g., as DQ[7:0]. The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, . . . , E, F) indicates a number expressed in hexadecimal notation. The designation 0bXXXX indicates a number expressed in binary notation (X = 0, 1).
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SIGNAL DESCRIPTIONS
Name A[17:0] Type Description Address, active High. In Word mode, these 18 inputs select one of 262,144 (256K) words within the array for read or write operations. In Byte mode, these Inputs inputs are combined with the DQ15/A-1 input (LSB) to select one of 524,288 (512K) bytes within the array for read or write operations. Data Bus, active High. In Word mode, these pins provide a 16-bit data path Inputs/Outputs for read and write operations. In Byte mode, DQ[7:0] provide an 8-bit data path Tri-state and DQ[15]/A[-1] is used as the LSB of the 19-bit byte address input. DQ[14:8] are unused and remain tri-stated in Byte mode. Byte Mode, active Low. Controls the Byte/Word configuration of the device. Input Low selects Byte mode, High selects Word mode. Chip Enable, active Low. This input must be asserted to read data from or Input write data to the HY29F400A. When High, the data bus is tri-stated and the device is placed in the Standby mode. Output Enable, active Low . This input must be asserted for read operations and negated for write operations. BYTE# determines whether a byte or a word Input is read during the read operation. When High, data outputs from the device are disabled and the data bus pins are placed in the high impedance state. W r ite E n a b le , a c tiv e L o w. C o ntro ls wri ti ng o f c o mma nd s o r c o mma nd sequences in order to program data or erase sectors of the memory array. A Input write operation takes place when WE# is asserted while CE# is Low and OE# is High. BYTE# determines whether a byte or a word is written during the write operation. Hardw are Reset, active Low. Provides a hardware method of resetting the HY29F400A to the read array state. When the device is reset, it immediately Input terminates any operation in progress. The data bus is tri-stated and all read/write commands are ignored while the input is asserted. While RESET# is asserted, the device will be in the Standby mode. R e a d y /B u s y S ta tu s . Ind i c a te s whe the r a wri te o r e ra s e c o mma nd i s i n progress or has been completed. RY/BY# is valid after the rising edge of the Output final WE# pulse of a command sequence. It remains Low while the device is Open Drain actively programming data or erasing, and goes High when it is ready to read array data. 5-volt (nominal) pow er supply. --Pow er and signal ground.
DQ[15]/A[-1], DQ[14:0] BYTE# C E#
OE#
WE#
RESET#
RY/BY#
VCC V SS
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HY29F400A
MEMORY ARRAY ORGANIZATION The 4 Mbit Flash memory array is organized into 11 blocks called sectors (S0, S1, . . . , S10). A sector is the smallest unit that can be erased and which can be protected to prevent accidental or unauthorized erasure. See the `Bus Operations' and `Command Definitions' sections of this document for additional information on these functions. In the HY29F400A, four of the sectors, which comprise the boot block, vary in size from 8 to 32 Kbytes (4 to 16 Kwords), while the remaining seven sectors are uniformly sized at 64 Kbytes (32 Kwords). The boot block can be located at the bottom of the address range (HY29F400AB) or at the top of the address range (HY29F400AT). Table 1 defines the sector addresses and corresponding address ranges for the top and bottom boot block versions of the HY29F400A. BUS OPERATIONS Device bus operations are initiated through the internal command register, which consists of sets of latches that store the commands, along with the address and data information, if any, needed to execute the specific command. The command register itself does not occupy any addressable memory location. The contents of the command register serve as inputs to an internal state machine whose outputs control the operation of the device. Table 2 lists the normal bus operations,
Table 1. HY29F400A Memory Array Organization
Device Sector S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 Sector Address Size (KB/KW) A[17] A[16] A[15] A[14] A[13] A[12] 64/32 64/32 64/32 64/32 64/32 64/32 64/32 32/16 8/4 8/4 16/8 16/8 8/4 8/4 32/16 64/32 64/32 64/32 64/32 64/32 64/32 64/32 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 0 0 0 0 1 0 1 0 1 0 1 X X X X X X X 0 1 1 1 0 0 0 1 X X X X X X X X X X X X X X X 0 0 1 0 1 1 X X X X X X X X X X X X X X X X 0 1 X X 0 1 X X X X X X X X Byte Mode Address Range 2 0x00000 - 0x0FFFF 0x10000 - 0x1FFFF 0x20000 - 0x2FFFF 0x30000 - 0x3FFFF 0x40000 - 0x4FFFF 0x50000 - 0x5FFFF 0x60000 - 0x6FFFF 0x70000 - 0x77FFF 0x78000 - 0x79FFF 0x7A000 - 0x7BFFF 0x7C000 - 0x7FFFF 0x00000 - 0x03FFF 0x04000 - 0x05FFF 0x06000 - 0x07FFF 0x08000 - 0x0FFFF 0x10000 - 0x1FFFF 0x20000 - 0x2FFFF 0x30000 - 0x3FFFF 0x40000 - 0x4FFFF 0x50000 - 0x5FFFF 0x60000 - 0x6FFFF 0x70000 - 0x7FFFF Word Mode Address Range 3 0x00000 - 0x07FFF 0x08000 - 0x0FFFF 0x10000 - 0x17FFF 0x18000 - 0x1FFFF 0x20000 - 0x27FFF 0x28000 - 0x2FFFF 0x30000 - 0x37FFF 0x38000 - 0x3BFFF 0x3C000 - 0x3CFFF 0x3D000 - 0x3DFFF 0x3E000 - 0x3FFFF 0x00000 - 0x01FFF 0x02000 - 0x02FFF 0x03000 - 0x03FFF 0x04000 - 0x07FFF 0x08000 - 0x0FFFF 0x10000 - 0x17FFF 0x18000 - 0x1FFFF 0x20000 - 0x27FFF 0x28000 - 0x2FFFF 0x30000 - 0x37FFF 0x38000 - 0x3FFFF
Notes: 1. X indicates Don't Care. 2. Address in Byte Mode is A[17:-1]. 3. Address in Word Mode is A[17:0].
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HY29F400AB - Bottom Boot Block
HY29F400AT - Top Boot Block
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HY29F400A
Table 2. HY29F400A Normal Bus Operations 1
Operation CE# OE# L H H X X X X WE# H L H X X X X RESET # H H H H VCC 0.5V L VSS 0.5V Address 2 AIN AIN X X X X X DQ[7:0] DOUT DIN High-Z High-Z High-Z High-Z High-Z DQ[15:8] 3 BYTE# = H BYTE# = L DOUT DIN High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z
Read L Write L Output Disable L CE# TTL Standby H CE# CMOS Standby VCC 0.5V Hardware Reset (TTL Standby) Hardware Reset (CMOS Standby) X X
Notes: 1. L = VIL, H = VIH, X = Don't Care, DOUT = Data Out, DIN = Data In. See DC Characteristics for voltage levels. 2. Address is A[17:-1] in Byte Mode and A[17:0] in Word Mode. 3. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).
the inputs and control levels they require, and the resulting outputs. Certain bus operations require a high voltage on one or more device pins. Those are described in Table 3. Read Operation Data is read from the HY29F400A by using standard microprocessor read cycles while placing the address of the byte or word to be read on the device's address inputs, A[17:0] in Word mode (BYTE# = H) or A[17:-1] in Byte mode (BYTE# = L) . As shown in Table 2, the host system must drive the CE# and OE# inputs Low and drive WE# High for a valid read operation to take place. The device outputs the specified array data on DQ[7:0] in Byte mode and on DQ[15:0] in Word mode. Note that DQ[15] serves as address input A[-1] when the device is operating in Byte mode. The HY29F400A is automatically set for reading array data after device power-up and after a hardware reset to ensure that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data, and the device remains enabled for read accesses until the command register contents are altered. This device features an Erase Suspend mode. While in this mode, the host may read the array data from any sector of memory that is not marked for erasure. If the host attempts to read from an address within an erase-suspended sector, or
while the device is performing an erase or byte/ word program operation, the device outputs status data instead of array data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exceptions noted above. After completing an internal program or internal erase algorithm, the HY29F400A automatically returns to the Read Array Data mode. The host must issue a hardware reset or the software reset command (see Command Definitions) to return a sector to the read array data mode if DQ[5] goes high during a program or erase cycle, or to return the device to the Read Array Data mode while it is in the Electronic ID mode. Write Operation Certain operations, including programming data and erasing sectors of memory, require the host to write a command or command sequence to the HY29F400A. Writes to the device are performed by placing the byte or word address on the device's address inputs while the data to be written is input on DQ[7:0] in Byte mode (BYTE# = L) and on DQ[15:0] in Word mode (BYTE# = H). The host system must drive the CE# and WE# pins Low and drive OE# High for a valid write operation to take place. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first.
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HY29F400A
Table 3. HY29F400A Bus Operations Requiring High Voltage
Operation 3 Sector Protect Sector Unprotect Temporary Sector Unprotect Manufacturer Code D evi ce HY29F400AB C ode HY29F400AT Sector Group Protection Verification
1, 2
DQ[15: 8] CE# OE# WE# RESET# A[17:12] A[9] A[6] A[1] A[0] L VID X L L VID VID X L L X X X H H H H VID H H SA 4 X X X X VID VID X VID VID X X X L L X X X L L X X X L H DQ[7: 0] X X DIN 0xAD 0xAB 0x23 0x00 = Unprotected 0x01 = Protected BYTE# BYTE# =H = L5 X X DIN X 0x22 High-Z High-Z High-Z High-Z High-Z
L
L
H
H
SA 4
VID
L
H
L
X
High-Z
Notes: 1. L = VIL, H = VIH, X = Don't Care. See DC Characteristics for voltage levels. 2. Address bits not specified are Don't Care. 3. See text for additional information. 4. SA = sector address. See Table 1. 5. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).
The `Device Commands' section of this document provides details on the specific device commands implemented in the HY29F400A. Output Disable Operation When the OE# input is at VIH, output data from the device is disabled and the data bus pins are placed in the high impedance state. Standby Operation When the system is not reading from or writing to the HY29F400A, it can place the device in the Standby mode. In this mode, current consumption is greatly reduced, and the data bus outputs are placed in the high impedance state, independent of the OE# input. The Standby mode can be invoked using two methods. The device enters the CE# CMOS Standby mode if the CE# and RESET# pins are both held at VCC 0.5V. Note that this is a more restricted voltage range than VIH. If both CE# and RESET# are held High, but not within VCC 0.5V, the device will be in the CE# TTL Standby mode, but the standby current will be greater. The device enters the RESET# CMOS Standby mode when the RESET# pin is held at VSS 0.5V. If RESET# is held Low but not within VSS 0.5V,
Rev. 1.0/Jan. 02
the HY29F400A will be in the RESET# TTL Standby mode, but the standby current will be greater. See Hardware Reset Operation section for additional information on the reset operation. The device requires standard access time (tCE) for read access when the device is in either of the standby modes, before it is ready to read data. If the device is deselected during erasure or programming, it continues to draw active current until the operation is completed. Hardware Reset Operation The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven Low for the minimum specified period, the device immediately terminates any operation in progress, tri-states the data bus pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. If an operation was interrupted by the assertion of RESET#, it should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. Current is reduced for the duration of the RESET# pulse as described in the Standby Operation section above.
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HY29F400A
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains Low (busy) until the internal reset operation is complete, which requires a time of tREADY (during Automatic Algorithms). The system can thus monitor RY/BY# to determine when the reset operation completes, and can perform a read or write operation tRB after RY/BY# goes High. If RESET# is asserted when a program or erase operation is not executing (RY/ BY# pin is High), the reset operation is completed within a time of tRP. In this case, the host can perform a read or write operation tRH after the RESET# pin returns High . The RESET# pin may be tied to the system reset signal. Thus, a system reset would also reset the device, enabling the system to read the boot-up firmware from the Flash memory. Sector Protect/Unprotect Operations Hardware sector protection can be invoked to disable program and erase operations in any single sector or combination of sectors. This function is typically used to protect data in the device from unauthorized or accidental attempts to program or erase the device while it is in the system (e.g., by a virus) and is implemented using programming equipment. Sector unprotection re-enables the program and erase operations in previously protected sectors. Table 1 identifies the eleven sectors and the address range that each covers for both versions of the device. The device is shipped with all sectors unprotected. The sector protect/unprotect operations require a high voltage (VID) on address pin A[9] and the CE# and/or OE# control pins, as detailed in Table 3. When implementing these operations, note that VCC must be applied to the device before applying VID, and that VID should be removed before removing VCC from the device. The flow chart in Figure 1 illustrates the procedure for protecting sectors, and timing specifications and waveforms are shown in the specifications section of this document. Verification of protection is accomplished as described in the Electronic ID Mode section and shown in the flow chart.
START Wait tWPP1 APPLY V CC WE# = VIH A[9] = V ID A[17:12] = Sector to Protect OE# = CE# = V IL A[6] = A[0] = V IL, A[1] = V IH Read Data Set A[9] = OE# = V ID NO NO
Set TRYCNT = 1
Increment TRYCNT
Data = 0x01? Set Address: A[17:12] = Sector to Protect CE# = V IL RESET# = V IH
TRYCNT = 25?
YES
YES Remove VID from A[9]
WE# = VIL
Protect Another Sector?
NO SECTOR PROTECT COMPLETE
DEVICE FAILURE YES
Figure 1. Sector Protect Procedure
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HY29F400A
The procedure for sector unprotection is illustrated in the flow chart in Figure 2, and timing specifications and waveforms are given at the end of this document. Note that to unprotect any sector, all unprotected sectors must first be protected prior to the first unprotect write cycle. Sectors can also be temporarily unprotected as described in the next section. Temporary Sector Unprotect Operation This feature allows temporary unprotection of previously protected sectors to allow changing the data in-system. Temporary Sector Unprotect mode is activated by setting the RESET# pin to VID. While in this mode, formerly protected sectors can be programmed or erased by invoking the appropriate commands (see Device Commands section). Once VID is removed from RESET#, all the previously protected sectors are protected again. Figure 3 illustrates the algorithm.
RESET# = V IH (All previously protected sector groups return to protected state) START
RESET# = V ID (All protected sector groups become unprotected)
Perform Program or Erase Operations
TEMPORARY SECTOR UNPROTECT COMPLETE
Figure 3. Temporary Sector Unprotect
START NOTE: All sectors must be previously protected. Set Sector Address: A[17:12] = Sector NSEC A[0] = A[6] = V IL A[1] = V IH Increment TRYCNT
APPLY V CC
Set: TRYCNT = 1 Read Data NO Set: NSEC = 0 Data = 0x00? Set: A[9] = CE# = OE# = V ID YES YES NO YES TRYCNT = 1000?
Set: RESET# = V IH
WE# = V IL
NSEC = 10?
Wait t WPP2
NO NSEC = NSEC + 1
Remove V ID from A[9]
WE# = V IH
SECTOR UNPROTECT COMPLETE
DEVICE FAILURE
Set: A[9] = V ID OE# = CE# = V IL
Figure 2. Sector Unprotect Procedure
Rev. 1.0/Jan. 02
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HY29F400A
Electronic ID Mode Operation The Electronic ID mode provides manufacturer and device identification and sector protection verification through identifier codes output on DQ[7:0] or DQ[15:0]. This mode is intended primarily for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. The Electronic ID information can also be obtained by the host through a command sequence, as described in the Device Commands section. Operation in the Electronic ID mode requires VID on address pin A[9], with additional requirements for obtaining specific data items as listed in Table 2: A read cycle at address 0xXXX00 retrieves the manufacturer code (Hynix = 0xAD). A read cycle at address 0xXXX01 returns the device code: - HY29F400AT = 0x23 in Byte mode, 0x2223 in Word mode. - HY29F400AB = 0xAB in Byte mode, 0x22AB in Word mode. A read cycle containing a sector address (Table 1) in A[17:12] and the address 0x02 in A[7:0] returns 0x01 if that sector is protected, or 0x00 if it is unprotected.
DEVICE COMMANDS Device operations are initiated by writing designated address and data command sequences into the device. A command sequence is composed of one, two or three of the following sub-segments: an unlock cycle, a command cycle and a data cycle. Table 4 summarizes the composition of the valid command sequences implemented in the HY29F400A, and these sequences are fully described in Table 5 and in the sections that follow. Writing incorrect address and data values or writing them in the improper sequence resets the HY29F400A to the Read mode. Read/Reset 1, 2 Commands The HY29F400A automatically enters the Read mode after device power-up, after the RESET# input is asserted and upon the completion of certain commands. Read/Reset commands are not required to retrieve data in these cases. A Read/Reset command must be issued in order to read array data in the following cases: If the device is in the Electronic ID mode, a Read/Reset command must be written to return to the Read mode. If the device was in the Erase Suspend mode when the device entered the Electronic ID mode, writing the Read/Reset command returns the device to the Erase Suspend mode. Table 4. Composition of Command Sequences
Co mman d Seq u en c e Read/Reset 1 Read/Reset 2 Byte Program Chip Erase Sector Erase Erase Suspend Erase Resume Electronic ID Nu mb er o f B u s Cy c les Un lo c k Co mman d 0 2 2 4 4 0 0 2 1 1 1 1 1 1 1 1 Dat a Note 1 Note 1 1 1 1 (Note 2) 0 0 Note 3
Notes: 1. Any number of Flash array read cycles are permitted. 2. Additional data cycles may follow. See text. 3. Any number of Electronic ID read cycles are permitted. Note: When in the Electronic ID bus operation mode, the device returns to the Read mode when VID is removed from the A[9] pin. The Read/Reset command is not required in this case.
If DQ[5] (Exceeded Time Limit) goes High during a program or erase operation, writing the Read/Reset command returns the sectors to the Read mode (or to the Erase Suspend mode if the device was in Erase Suspend). The Read/Reset command may also be used to abort certain command sequences:
Rev. 1.0/Jan. 02
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Table 5. HY29F400A Command Sequences
Bus Cycles 1, 2, 3 T hird Fourth Add Data Add Data Fifth Add Data Sixth Add Data
Electronic ID 7
Rev. 1.0/Jan. 02
Command Sequence
Read/Reset 1 6, 8 F0 A0 80 80 AA AA PA PD 55 55 RA RD
Reset/Reset 2
7, 8
Program
Chip Erase
555 AAA SA
10 30
Sector Erase
Word Byte Word Byte Word Byte Word Byte 555 AAA 555 AAA 2AA 555 2AA 555
Second Add Data RA RD 2AA 55 555 2AA 55 555 2AA 55 555 2AA 55 555 555 AAA 555 AAA 555 AAA 555 AAA
Erase Suspend 4 Erase Resume 5 55 55 55 90 90 90 X00
Manufacturer Code
AD X01 2223 (Top Boot), 22AB (Bottom Boot) X02 23 (Top Boot), AB (Bottom Boot)
Device Code
Sector Protect Verify
(SA)X02 (SA)X04
Word Byte Word Byte Word Byte
First Write Cycles Add Data 1 XXX F0 555 3 AA AAA 555 4 AA AAA 555 6 AA AAA 555 6 AA AAA 1 XXX B0 1 XXX 30 555 3 AA AAA 555 3 AA AAA 555 3 AA AAA 2AA 555 2AA 555 2AA 555 555 AAA 555 AAA 555 AAA
STATUS
Legend: X = Don't Care PA = Address of the data to be programmed RA = Memory address of data to be read PD = Data to be programmed at address PA RD = Data read from location RA during the read operation SA = Sector address of sector to be erased or verified (see Note 3 and Table 1). STATUS = Sector protect status: 0x00 = unprotected, 0x01 = protected.
Notes: 1. All values are in hexadecimal. DQ[15:8] are don't care for unlock and command cycles. 2. All bus cycles are write operations unless otherwise noted. 3. Address is A[10:0] in Word mode and A[10:-1] in Byte mode. A[17:11] are don't care except as follows: * For RA and PA, A[17:11] are the upper address bits of the byte to be read or programmed. * For the sixth cycle of Sector Erase, SA = A[17:12] are the sector address of the sector to be erased. * For the fourth cycle of Sector Protect Verify, SA = A[17:12] are the sector address of the sector to be verified. 4. The Erase Suspend command is valid only during a sector erase operation. The system may read and program in non-erasing sectors, or enter the Electronic ID mode, while in the Erase Suspend mode. 5. The Erase Resume command is valid only during the Erase Suspend mode. 6. The second bus cycle is a read cycle. 7. The fourth bus cycle is a read cycle. 8. Either command sequence is valid. The command is required only to return to the Read mode when the device is in the Electronic ID command mode or if DQ[5] goes High during a program or erase operation. It is not required for normal read operations.
HY29F400A
11
HY29F400A
In a Sector Erase or Chip Erase command sequence, the Read/Reset command may be written at any time before erasing actually begins, including, for the Sector Erase command, between the cycles that specify the sectors to be erased (see Sector Erase command description). This aborts the command and resets the device to the Read mode. Once erasure begins, however, the device ignores Read/ Reset commands until the operation is complete. In a Program command sequence, the Read/ Reset command may be written between the sequence cycles before programming actually begins. This aborts the command and resets the device to the Read mode, or to the Erase Suspend mode if the Program command sequence is written while the device is in the Erase Suspend mode. Once programming begins, however, the device ignores Read/Reset commands until the operation is complete. The Read/Reset command may be written between the cycles in an Electronic ID command sequence to abort that command. As described above, once in the Electronic ID mode, the Read/Reset command must be written to return to the Read mode. Byte/Word Program Command The host processor programs the device a byte or word at a time by issuing the Program command sequence shown in Table 5. The sequence begins by writing two unlock cycles, followed by the Program setup command and, lastly, a data cycle specifying the program address and data. This initiates the Automatic Programming algorithm, which provides internally generated program pulses and verifies the programmed cell margin. The host is not required to provide further controls or timings during this operation. When the Automatic Programming algorithm is complete, the device returns to the Read mode. Several methods are provided to allow the host to determine the status of the programming operation, as described in the Write Operation Status section. Commands written to the device during execution of the Automatic Programming algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. To ensure data integrity, the aborted program command se12
quence should be reinitiated once the reset operation is complete. Programming is allowed in any sequence. Only erase operations can convert a stored "0" to a "1". Thus, a bit cannot be programmed from a "0" back to a "1". Attempting to do so will set DQ[5] to "1", and the Data# Polling algorithm will indicate that the operation was not successful. A Read/Reset command or a hardware reset is required to exit this state, and a succeeding read will show that the data is still "0". Figure 4 illustrates the procedure for the Byte/Word Program operation. Chip Erase Command The Chip Erase command sequence consists of two unlock cycles, followed by the erase command, two additional unlock cycles and then the chip erase data cycle. During chip erase, all sectors of the device are erased except protected sectors. The command sequence starts the Automatic Erase algorithm, which preprograms and verifies the entire memory, except for protected sectors, for an all zero data pattern prior to electrical erase. The device then provides the required number of internally generated erase pulses and verifies cell erasure within the proper cell margins. The host system is not required to provide any controls or timings during these operations.
START
Issue PROGRAM Command Sequence: Last cycle contains program Address/Data
Check Programming Status (See Write Operation Status Section) Normal Exit
DQ[5] Error Exit
NO
Last Word/Byte Done?
YES PROGRAMMING COMPLETE GO TO ERROR RECOVERY
Figure 4. Programming Procedure
Rev. 1.0/Jan. 02
HY29F400A
Commands written to the device during execution of the Automatic Erase algorithm are ignored. Note that a hardware reset immediately terminates the erase operation. To ensure data integrity, the aborted Chip Erase command sequence should be reissued once the reset operation is complete. When the Automatic Erase algorithm is finished, the device returns to the Read mode. Several methods are provided to allow the host to determine the status of the erase operation, as described in the Write Operation Status section. Figure 5 illustrates the Chip Erase procedure. Sector Erase Command The Sector Erase command sequence consists of two unlock cycles, followed by the erase command, two additional unlock cycles and then the sector erase data cycle, which specifies which sector is to be erased. As described later in this section, multiple sectors can be specified for erasure with a single command sequence. During sector erase, all specified sectors are erased sequentially. The data in sectors not specified for erasure, as well as the data in any protected sectors, even if specified for erasure, is not affected by the sector erase operation. The Sector Erase command sequence starts the Automatic Erase algorithm, which preprograms and verifies the specified unprotected sectors for an all zero data pattern prior to electrical erase. The device then provides the required number of internally generated erase pulses and verifies cell erasure within the proper cell margins. The host system is not required to provide any controls or timings during these operations. After the sector erase data cycle (the sixth bus cycle) of the command sequence is issued, a sector erase time-out of 50 s, measured from the rising edge of the final WE# pulse in that bus cycle, begins. During this time, an additional sector erase data cycle, specifying the sector address of another sector to be erased, may be written into an internal sector erase buffer. This buffer may be loaded in any sequence, and the number of sectors specified may be from one sector to all sectors. The only restriction is that the time between these additional data cycles must be less than 50 s, otherwise erasure may begin before the last data cycle is accepted. To ensure that all data cycles are accepted, it is recommended that host processor interrupts be disabled during the time that the additional cycles are being issued and then be re-enabled afterwards.
Note: The device is capable of accepting three ways of invoking Erase Commands for additional sectors during the time-out window. The preferred method, described above, is the sector erase data cycle after the initial six bus cycle command sequence. However, the HY29F400A also accepts the following methods of specifying additional sectors during the sector erase time-out: Repeat the entire six-cycle command sequence, specifying the additional sector in the sixth cycle. Repeat the last three cycles of the six-cycle command sequence, specifying the additional sector in the third cycle.
START
If all sectors scheduled for erasing are protected, the device returns to reading array data after approximately 100 s. If at least one scheduled sector is not protected, the erase operation erases the unprotected sectors, and ignores the command for the scheduled sectors that are protected. The system can monitor DQ[3] to determine if the 50 s sector erase time-out has expired, as described in the Write Operation Status section. If the time between additional sector erase data cycles can be insured to be less than the timeout, the system need not monitor DQ[3]. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must then rewrite the command sequence, including any additional sector erase data cycles. Once the sector erase operation itself has begun, only the Erase
13
Issue CHIP ERASE Command Sequence
Check Erase Status (See Write Operation Status Section) Normal Exit
DQ[5] Error Exit
CHIP ERASE COMPLETE
GO TO ERROR RECOVERY
Figure 5. Chip Erase Procedure
Rev. 1.0/Jan. 02
HY29F400A
Suspend command is valid. All other commands are ignored. As for the Chip Erase command, note that a hardware reset immediately terminates the erase operation. To ensure data integrity, the aborted Sector Erase command sequence should be reissued once the reset operation is complete. When the Automatic Erase algorithm terminates, the device returns to the Read mode. Several methods are provided to allow the host to determine the status of the erase operation, as described in the Write Operation Status section. Figure 6 illustrates the Sector Erase procedure. Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation to read data from, or program data to, any sector not being erased. The command causes the erase operation to be suspended in all sectors selected for erasure. This command is valid only during the sector erase operation, including during the 50 s time-out period at the end of the initial command sequence and any subsequent sector erase data cycles, and is ignored if it is issued during chip erase or programming operations. The HY29F400A requires a maximum of 20 s to suspend the erase operation if the Erase Suspend command is issued during active sector erasure. However, if the command is written during the timeout, the time-out is terminated and the erase operation is suspended immediately. Any subsequent attempts to specify additional sectors for erasure by writing the sector erase data cycle (SA/ 0x30) will be interpreted as the Erase Resume command (XXX/0x30), which will cause the Automatic Erase algorithm to begin its operation. Note that any other command during the time-out will reset the device to the Read mode. Once the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. Normal read and write timings and command definitions apply. Reading at any address within erasesuspended sectors produces status data on DQ[7:0]. The host can use DQ[7], or DQ[6] and DQ[2] together, to determine if a sector is actively erasing or is erase-suspended. See "Write Operation Status" for information on these status bits.
START Check Erase Status DQ[5] Error Exit (See Write Operation Status Section) Normal Exit Write First Five Cycles of SECTOR ERASE Command Sequence ERASE COMPLETE Setup First (or Next) Sector Address for Erase Operation GO TO ERROR RECOVERY
Write Last Cycle (SA/0x30) of SECTOR ERASE Command Sequence NO Sector Erase Time-out (DQ[3]) Expired?
Sectors which require erasure but which were not specified in this erase cycle must be erased later using a new command sequence
Erase An Additional Sector?
YES
YES
NO
Figure 6. Sector Erase Procedure
14
Rev. 1.0/Jan. 02
HY29F400A
After an erase-suspended program operation is complete, the host can initiate another programming operation (or read operation) within non-suspended sectors. The host can determine the status of a program operation during the erase-suspended state just as in the standard programming operation. The system must write the Erase Resume command to exit the Erase Suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. The host may also write the Electronic ID command sequence when the device is in the Erase Suspend mode. The device allows reading Electronic ID codes even if the addresses used for the ID read cycles are within erasing sectors, since the codes are not stored in the memory array. When the device exits the Electronic ID mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See Electronic ID section for more information. Electronic ID Command The Electronic ID operation intended for use in programming equipment has been described previously. The host processor can also be obtain the same data by using the Electronic ID command sequence shown in Table 5. This method does not require VID on any pin. The Electronic ID command sequence may be invoked while the device is in the Read mode or the Erase Suspend mode, WRITE OPERATION STATUS The HY29F400A provides a number of facilities to determine the status of a program or erase operation. These are the RY/BY# (Ready/Busy#) pin and certain bits of a status word which can be read from the device during the programming and erase operations. Table 6 summarizes the status indications and further detail is provided in the subsections which follow. RY/BY# - Ready/Busy# RY/BY# is an open-drain output pin that indicates whether a programming or erase Automatic Algorithm is in progress or has completed. A pull-up resistor to VCC is required for proper operation. RY/
Rev. 1.0/Jan. 02
but is invalid while the device is actively programming or erasing. The Electronic ID command sequence is initiated by writing two unlock cycles, followed by the Electronic ID command. The device then enters the Electronic ID mode, and: A read cycle at address 0xXXX00 retrieves the manufacturer code (Hynix = 0xAD). In Word mode, a read cycle at address 0xXXX01 returns the device code (HY29F400AT = 0x2223, HY29F400AB = 0x22AB). In Byte mode, the same information is retrieved from address 0xXXX02 (HY29F400AT = 0x23, HY29F400AB = 0xAB). In Word mode, a read cycle containing a sector address in A[17:12] and the address 0x02 in A[7:0] returns 0xXX01 if that sector is protected, or 0xXX00 if it is unprotected. In Byte mode, the status information is retrieved using 0x04 in A[6:-1] (0x01 if the sector is protected, 0x00 if the sector is unprotected). The host system may read at any address any number of times, without initiating another command sequence. Thus, for example, the host may determine the protection status for all sectors by doing successive reads at the address specified above while changing the sector address for each cycle. The system must write the Reset command to exit the Electronic ID mode and return to the Read mode, or to the Erase Suspend mode if the device was in that mode when the command sequence was issued. BY# is valid after the rising edge of the final WE# pulse in the corresponding command sequence. If the output is Low (busy), the device is actively erasing or programming, including programming while in the Erase Suspend mode. If the output is High (ready), the device has completed the operation and is ready to read array data in the normal or Erase Suspend modes, or it is in the standby mode. DQ[7] - Data# Polling The Data# ("Data Bar") Polling bit, DQ[7], indicates to the host system whether an Automatic Algo15
HY29F400A
Table 6. Write and Erase Operation Status Summary
Mo d e Op er at io n Programming in progress Normal Programming completed Erase in progress Erase completed Read within erase suspended sector Read within non-erase Erase Suspend suspended sector Programming in progress 5 Programming completed
5
DQ[ 7] Data 0 1 1 Data
1
DQ[ 6] Toggle Data Data
4
DQ[ 5] 0/1 0/1
2
DQ[ 3] N/A Data 1
3
DQ[ 2] N/A Data
1
RY/B Y# 0 1 0 1 1 1 0 1
DQ[7]#
Data
2
Toggle
4
Toggle Data
4
Data 0 Data 0/1 2 Data
Data N/A Data N/A Data
No toggle Data Toggle Data
4
Toggle Data N/A Data
DQ[7]# Data
Notes: 1. A valid address is required when reading status information. See text for additional information. 2. DQ[5] status switches to a `1' when a program or erase operation exceeds the maximum timing limit. 3. A `1' during sector erase indicates that the 50 s time-out has expired and active erasure is in progress. DQ[3] is not applicable to the chip erase operation. 4. Equivalent to `No Toggle' because data is obtained in this state. 5. Programming can be done only in a non-suspended sector (a sector not marked for erasure).
rithm is in progress or completed, or whether the device is in Erase Suspend mode. Data# Polling is valid after the rising edge of the final WE# pulse in the Program or Erase command sequence. The system must do a read at the program address to obtain valid programming status information on this bit. While a programming operation is in progress, the device outputs the complement of the value programmed to DQ[7]. When the programming operation is complete, the device outputs the value programmed to DQ[7]. If a program operation is attempted within a protected sector, Data# Polling on DQ[7] is active for approximately 2 s, then the device returns to reading array data. The host must read at an address within any nonprotected sector scheduled for erasure to obtain valid erase status information on DQ[7]. During an erase operation, Data# Polling produces a "0" on DQ[7]. When the erase operation is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ[7]. If all sectors selected for erasing are protected, Data# Polling on DQ[7] is active for approximately 100 s, then the device returns to reading array data. If at least one selected sector is not protected, the erase operation erases the unprotected sectors, and ignores the command for the selected sectors that are protected.
When the system detects that DQ[7] has changed from the complement to true data (or "0" to "1" for erase), it should do an additional read cycle to read valid data from DQ[7:0]. This is because DQ[7] may change asynchronously with respect to the other data bits while Output Enable (OE#) is asserted low. Figure 7 illustrates the Data# Polling test algorithm. DQ[6] - Toggle Bit I Toggle Bit I on DQ[6] indicates whether an Automatic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the program or erase command sequence, including during the sector erase time-out. The system may use either OE# or CE# to control the read cycles. Successive read cycles at any address during an Automatic Program algorithm operation (including programming while in Erase Suspend mode) cause DQ[6] to toggle. DQ[6] stops toggling when the operation is complete. If a program address falls within a protected sector, DQ[6] toggles for approximately 2 s after the program command sequence is written, then returns to reading array data. While the Automatic Erase algorithm is operating, successive read cycles at any address cause
Rev. 1.0/Jan. 02
16
HY29F400A
DQ[6] to toggle. DQ[6] stops toggling when the erase operation is complete or when the device is placed in the Erase Suspend mode. The host may use DQ[2] to determine which sectors are erasing or erase-suspended (see below). After an Erase command sequence is written, if all sectors selected for erasing are protected, DQ[6] toggles for approximately 100 s, then returns to reading array data. If at least one selected sector is not protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
NO START
Read DQ[7:0] at Valid Address (Note 1) Test for DQ[7] = 1? for Erase Operation DQ[7] = Data? YES
NO
DQ[2] - Toggle Bit II Toggle Bit II, DQ[2], when used with DQ[6], indicates whether a particular sector is actively erasing or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. The device toggles DQ[2] with each OE# or CE# read cycle. DQ[2] toggles when the host reads at addresses within sectors that have been selected for erasure, but cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ[6], by comparison, indicates whether the device is actively erasing or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Figure 8 illustrates the operation of Toggle Bits I and II. DQ[5] - Exceeded Timing Limits DQ[5] is set to a `1' when the program or erase time has exceeded a specified internal pulse count limit. This is a failure condition that indicates that the program or erase cycle was not successfully completed. DQ[5] status is valid only while DQ[7] or DQ[6] indicate that the Automatic Algorithm is in progress. The DQ[5] failure condition will also be signaled if the host tries to program a `1' to a location that is previously programmed to `0', since only an erase operation can change a `0' to a `1'. For both of these conditions, the host must issue a Read/Reset command to return the device to the Read mode.
DQ[5] = 1?
YES Read DQ[7:0] at Valid Address (Note 1) Test for DQ[7] = 1? for Erase Operation DQ[7] = Data? (Note 2)
YES
NO PROGRAM/ERASE EXCEEDED TIME ERROR PROGRAM/ERASE COMPLETE
Notes: 1. During programming, the program address. During sector erase, an address within any non-protected sector scheduled for erasure. During chip erase, an address within any non-protected sector. 2. Recheck DQ[7] since it may change asynchronously at the same time as DQ[5].
Figure 7. Data# Polling Test Algorithm DQ[3] - Sector Erase Timer After writing a Sector Erase command sequence, the host may read DQ[3] to determine whether or not an erase operation has begun. When the sector erase time-out expires and the sector erase operation commences, DQ[3] switches from a `0' to a `1'. Refer to the "Sector Erase Command" section for additional information. Note that the sector erase timer does not apply to the Chip Erase command. After the initial Sector Erase command sequence is issued, the system should read the status on DQ[7] (Data# Polling) or DQ[6] (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ[3]. If DQ[3] is a `1', the internally controlled erase cycle has begun and
17
Rev. 1.0/Jan. 02
HY29F400A
START
DQ[5] = 1? Read DQ[7:0] at Valid Address (Note 1) NO YES Read DQ[7:0] at Valid Address (Note 1) Read DQ[7:0] at Valid Address (Note 1) Read DQ[7:0] Read DQ[7:0]
YES NO (Note 4) DQ[6] Toggled?
NO
DQ[6] Toggled? (Note 2)
NO DQ[2] Toggled?
NO (Note 3) PROGRAM/ERASE COMPLETE
YES PROGRAM/ERASE EXCEEDED TIME ERROR
YES SECTOR BEING READ IS IN ERASE SUSPEND SECTOR BEING READ IS NOT IN ERASE SUSPEND
Notes: 1. During programming, the program address. During sector erase, an address within any sector scheduled for erasure. 2. Recheck DQ[6] since toggling may stop at the same time as DQ[5] changes from 0 to 1. 3. Use this path if testing for Program/Erase status. 4. Use this path to test whether sector is in Erase Suspend mode.
Figure 8. Toggle Bit I and II Test Algorithm all further sector erase data cycles or commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ[3] is a `0', the device will accept a sector erase data cycle to mark an additional sector for erasure. To ensure that HARDWARE DATA PROTECTION The HY29F400A provides several methods of protection to prevent accidental erasure or programming which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. These methods are described in the sections that follow. Command Sequences Commands that may alter array data require a sequence of cycles as described in Table 5. This provides data protection against inadvertent writes. Low VCC Write Inhibit To protect data during VCC power-up and powerdown, the device does not accept write cycles when VCC is less than VLKO (typically 3.7 volts). The
18
the data cycles have been accepted, the system software should check the status of DQ[3] prior to and following each subsequent sector erase data cycle. If DQ[3] is high on the second status check, the last data cycle might not have been accepted. command register and all internal program/erase circuits are disabled, and the device resets to the Read mode. Writes are ignored until VCC is greater than VLKO . The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by asserting any one of the following conditions: OE# = VIL , CE# = VIH, or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one.
Rev. 1.0/Jan. 02
HY29F400A
Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the Read mode on powerup. Sector Protection Additional data protection is provided by the HY29F400A's sector protect feature, described previously, which can be used to protect sensitive areas of the Flash array from accidental or unauthorized attempts to alter the data.
Rev. 1.0/Jan. 02
19
HY29F400A
ABSOLUTE MAXIMUM RATINGS 4
Symbol TSTG TBIAS VIN2 I OS Storage Temperature Ambient Temperature with Power Applied Voltage on Pin with Respect to VSS : VCC 1 A[9], OE#, RESET# 2 All Other Pins 1 Output Short Circuit Current 3 Parameter Value -65 to +125 -55 to +125 -2.0 to +7.0 -2.0 to +12.5 -2.0 to +7.0 200 Unit C C V V V mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 10. 2. Minimum DC input voltage on pins A[9], OE#, and RESET# is -0.5 V. During voltage transitions, A[9], OE#, and RESET# may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on these pins is +12.5 V which may overshoot to 13.5 V for periods up to 20 ns. 3. No more than one output at a time may be shorted to VSS. Duration of the short circuit should be less than one second. 4. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS 1
Symbol TA V CC Parameter Ambient Operating Temperature Operating Supply Voltage: -50 Versions All Other Versions Value 0 to +70 +4.75 to +5.25 +4.50 to +5.50 Unit C V V
Notes: 1. Recommended Operating Conditions define those limits between which the functionality of the device is guaranteed.
20 ns 0.8 V - 0.5 V
20 ns
VCC + 2.0 V
20 ns
VCC + 0.5 V
- 2.0 V 20 ns
2.0 V 20 ns 20 ns
Figure 9. Maximum Undershoot Waveform
Figure 10. Maximum Overshoot Waveform
20
Rev. 1.0/Jan. 02
HY29F400A
DC CHARACTERISTICS TTL/NMOS Compatible
Parameter ILI ILIT ILO Description Input Load Current Input Load Current A[9], OE#, RESET# Output Leakage Current Test Setup VIN = VSS to VCC, VCC = VCC Max VCC = VCC Max; A[9] = OE# = RESET# = 12.5 V VOUT = VSS to VCC, VCC = VCC Max CE# = VIL, OE# = VIH, f = 5MHz, Byte Mode CE# = VIL, OE# = VIH, f = 5MHz, Word Mode CE# = VIL, OE# = VIH OE# = CE# = RESET# = VIH Min Typ Max 1.0 50 1.0 19 19 36 0.4 0.4 -0.5 2.0 11.5 40 50 60 1.0 1.0 0.8 VCC + 0.5 12.5 0.45 2.4 3.2 4.2 Unit A A A mA mA mA mA mA V V V V V V
ICC1 ICC2 ICC3 ICC4 VIL VIH VID VOL VOH VLKO
VCC Active Read Current
1, 2
VCC Active Write Current 2, 3, 4 VCC CE# Controlled TTL Standby Current 2 VCC RESET# Controlled RESET# = VIL TTL Standby Current 2 Input Low Voltage Input High Voltage Voltage for Electronic ID and VCC = 5.0V Temporary Sector Unprotect VCC = VCC Min, Output Low Voltage IOL = 5.8 mA VCC = VCC Min, Output High Voltage IOH = -2.5 mA Low VCC Lockout Voltage4
Notes: 1. The ICC current is listed is typically less than 2 mA/MHz with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCC Max. 3. ICC active while the Automatic Erase or Automatic Program algorithm is in progress. 4. Not 100% tested.
Rev. 1.0/Jan. 02
21
HY29F400A
DC CHARACTERISTICS CMOS Compatible
Parameter ILI ILIT ILO Description Input Load Current Input Load Current A[9], OE#, RESET# Output Leakage Current Test Setup VIN = VSS to VCC, VCC = VCC Max VCC = VCC Max, A[9] = OE# = RESET# =12.5 V VOUT = VSS to VCC, VCC = VCC Max CE# = VIL, OE# = VIH, f = 5MHz, Byte Mode CE# = VIL, OE# = VIH, f = 5MHz, Word Mode CE# = VIL, OE# = VIH VCC = VCC Max, CE# = RESET# = VCC 0.5V VCC = VCC Max, RESET# = VSS 0.5V -0.5 0.7 x VCC VCC = 5.0V VCC = VCC Min, IOL = 5.8 mA VCC = VCC Min, IOH = -2.5 mA VCC = VCC Min, IOH = -100 A 0.85 x VCC VCC - 0.4 3.2 4.2 11.5 20 28 30 0.3 0.3 Min Typ Max 1.0 50 1.0 40 50 50 5 5 0.8 VCC + 0.3 12.5 0.45 Unit A A A mA mA mA A A V V V V V V V
ICC1 ICC2 ICC3 ICC4 VIL VIH VID VOL
VCC Active Read Current 1, 2 VCC Active Write Current 2, 3, 4 VCC CE# Controlled CMOS Standby Current 2, 5 VCC RESET# Controlled CMOS Standby Current 2, 5 Input Low Voltage Input High Voltage Voltage for Electronic ID and Temporary Sector Unprotect Output Low Voltage
VOH
Output High Voltage
VLKO
Low VCC Lockout Voltage 3
Notes: 1. The ICC current is listed is typically less than 2 mA/MHz with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCC Max. 3. ICC active while the Automatic Erase or Automatic Program algorithm is in progress. 4. Not 100% tested. 5. ICC3 = 20 A maximum for industrial and extended temperature versions.
22
Rev. 1.0/Jan. 02
HY29F400A
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUT S Steady OUT PUT S
Changing from H to L
Changing from L to H
Don't Care, Any Change Permitted
Changing, State Unknown Centerline is High Impedance State (High Z)
Does Not Apply
TEST CONDITIONS
+ 5V
Table 7. Test Specifications
2.7 KOhm
Test Condition Output Load Output Load Capacitance (CL) Input Rise and Fall Times Input Signal Low Level Input Signal High Level Low Timing Measurement Signal Level High Timing Measurement Signal Level
- 50 - 70 - 55 Unit with Vcc 3/4 % 5 - 90 1 TTL Gate 30 5 0.0 3.0 1.5 1.5 30 5 3.0 1.5 1.5 100 pF 20 2.4 0.8 2.0 ns V V V V
DEVICE UNDER TEST CL 6.2 KOhm
All diodes are 1N3064 or equivalent
0.0 0.45
Figure 11. Test Setup
3.0 V Input 0.0 V 1.5 V
Measurement Level
1.5 V
Output
HY29F400A-50, 55 Version
2.4 V Input 0.45 V 0.8 V 2.0 V 2.0 V Output 0.8 V
Measurement Levels
HY29F400A-70, -90 Versions Figure 12. Input Waveforms and Measurement Levels
Rev. 1.0/Jan. 02
23
HY29F400A
AC CHARACTERISTICS Read Operations
Parameter JE D E C tAVAV tAVQV tELQV tEHQZ tGLQV tGHQZ Std tRC tACC tCE tDF tOE tDF tOEH tAXQX tOH Description Read Cycle Time 1 Address to Output Delay Chip Enable to Output Delay Chip Enable to Output High Z 1 Output Enable to Output Delay Output Enable to Output High Z 1 Read Output Enable Toggle and Hold Time 1 Data# Polling Output Hold Time from Addresses, CE# or OE#, Whichever Occurs First 1 CE# = VIL OE# = VIL OE# = VIL CE# = VIL Test Setup Min Max Max Max Max Max Min Min Min Speed Option - 50 - 55 50 50 50 15 25 15 55 55 55 15 25 15 0 10 0 - 70 70 70 70 20 30 20 - 90 90 90 90 20 35 20 Unit ns ns ns ns ns ns ns ns ns
Notes: 1. Not 100% tested.
tRC Addresses Addresses Stable tACC CE# tOE OE# tOEH WE# tCE tDF
tOH Output Valid
Outputs
RESET#
RY/BY#
0V
Figure 13. Read Operation Timings
24
Rev. 1.0/Jan. 02
HY29F400A
AC CHARACTERISTICS Hardware Reset (RESET#)
Parameter JE D E C Std tREADY tREADY tRP tRH tRB Description RESET# Pin Low (During Automatic Algorithms) to Read or Write 1 RESET# Pin Low (NOT During Automatic Algorithms) to Read or Write 1 RESET# Pulse Width RESET# High Time Before Read 1 RY/BY# Recovery Time Test Setup Max Max Min Min Min Speed Option - 50 - 55 - 70 20 500 500 50 0 - 90 Unit s ns ns ns ns
Notes: 1. Not 100% tested.
RY/BY# CE#, OE#
0V
tRH RESET# tRP tReady
Reset Timings NOT During Automatic Algorithms
RY/BY# CE#, OE# RESET# tRP
tReady tRB
Reset Timings During Automatic Algorithms Figure 14. RESET# Timings
Rev. 1.0/Jan. 02
25
HY29F400A
AC CHARACTERISTICS Word/Byte Configuration (BYTE#)
Parameter JE D E C Std tELFL tELFH tFLQZ tFHQV Description CE# to BYTE# Switching Low CE# to BYTE# Switching High BYTE# Switching Low to Output High-Z BYTE# Switching High to Output Active Max Max Max Min Speed Option - 50 - 55 5 5 15 50 15 55 20 70 20 90 - 70 - 90 Unit ns ns ns ns
CE# OE# BYTE# BYTE# switching from word to byte mode DQ[14:0] DQ[15]/A-1 tFLQZ BYTE# DQ[14:0]
Data Output DQ[7:0] Data Output DQ[14:0]
tELFL
Data Output DQ[14:0] Data Output DQ[7:0]
Output DQ[15]
Address Input A-1
BYTE# switching from byte to word mode
DQ[15]/A-1 tELFH
Address Input A-1
Data Output DQ[15]
tFHQV
Figure 15. BYTE# Timings for Read Operations
CE# Falling edge of the last WE# signal WE# tSET (tAS) BYTE#
Note: Refer to the Program/Erase Operations table for tAS and tAH specifications.
tHOLD (tAH)
Figure 16. BYTE# Timings for Write Operations
26
Rev. 1.0/Jan. 02
HY29F400A
AC CHARACTERISTICS Program and Erase Operations
Parameter JE D E C tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tELWL tWHEH tWLWH tWHWL Std tWC tAS tAH tDS tDH tGHWL tCS tCH tWP tWPH Description Write Cycle Time 1 Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Byte Mode tWHWH1 tWHWH1 Programming Operation 1, 2, 3 Word Mode Byte Mode Chip Programming Operation 1, 2, 3, 5 Word Mode Min Min Min Min Min Min Min Min Min Min Typ Max Typ Max Typ Max Typ Max Typ Max Typ Max Typ Min Min Min Min Speed Option - 50 - 55 50 50 25 55 0 45 25 0 0 0 0 30 30 35 45 20 7 300 12 500 3.6 10.8 3.1 9.3 1 8 11 88 1,000,000 100,000 50 0 30 30 45 30 45 45 - 70 70 - 90 90 Unit ns ns ns ns ns ns ns ns ns ns s s s s se c se c se c se c se c se c se c se c cycles cycles s ns ns
tWHWH2 tWHWH3
tWHWH2 Sector Erase Operation 1, 2, 4 tWHWH3 Chip Erase Operation 1, 2, 4 Erase and Program Cycle Endurance tVCS tRB tBUSY VCC Setup Time Recovery Time from RY/BY# WE# to RY/BY# Delay
30
35
Notes: 1. Not 100% tested. 2. Typical program and erase times assume the following conditions: 25 C, VCC = 5.0 volts, 100,000 cycles. In addition, programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case conditions of 90 C, VCC = 4.5 volts (4.75 volts for 55 ns version), 100,000 cycles. 3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program command. See Table 5 for further information on command sequences. 4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes are programmed to 0x00 before erasure. 5. The typical chip programming time is considerably less than the maximum chip programming time listed since most bytes program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum byte program time specified is exceeded. See Write Operation Status section for additional information.
Rev. 1.0/Jan. 02
27
HY29F400A
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
Read Status Data (last two cycles)
tWC Addresses CE# tGHWL OE# WE# tCS tDS 0xA0 tWP 0x555
tAS
tAH PA PA PA
tCH tWPH tDH tWHWH1 PD tBUSY Status DOUT tRB
Data
RY/BY# VCC tVCS
Notes: 1. PA = Program Address, PD = Program Data, DOUT is the true data at the program address. 2. Commands shown are for Word mode operation. 3. VCC shown only to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence.
Figure 17. Program Operation Timings
28
Rev. 1.0/Jan. 02
HY29F400A
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
Read Status Data (last two cycles)
tWC Addresses CE# tGHWL OE# tWP WE# tCS tDS tCH 0x2AA
tAS
tAH SA
Address = 0x555 for chip erase
VA
VA
tWPH tDH
Data = 0x10 for chip erase
tWHWH2 or tWHWH3 Status DOUT tRB
Data
0x55
0x30 tBUSY
RY/BY# VCC tVCS
Notes: 1. SA =Sector Address (for sector erase), VA = Valid Address for reading status data (see Write Operation Status section), DOUT is the true data at the read address.(0xFF after an erase operation). 2. Commands shown are for Word mode operation. 3. VCC shown only to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence.
Figure 18. Sector/Chip Erase Operation Timings
Rev. 1.0/Jan. 02
29
HY29F400A
AC CHARACTERISTICS
tRC Addresses tCH CE# tCE OE# tOEH WE# tOE tDF tOH
Complement Complement True Valid Data
VA tACC
VA
VA
DQ[7] DQ[6:0] tBUSY RY/BY#
Status Data
Status Data
Data
Valid Data
Notes: 1. VA = Valid Address for reading Data# Polling status data (see Write Operation Status section). 2. Illustration shows first status cycle after command sequence, last status read cycle and array data read cycle.
Figure 19. Data# Polling Timings (During Automatic Algorithms)
tRC Addresses tCH CE# tCE OE# tOEH WE# tOE tDF tOH
Valid Status Valid Status (second read) Valid Status (stops toggling) Valid Data
VA tACC
VA
VA
VA
DQ[6], [2] tBUSY RY/BY#
(first read)
Notes: 1. VA = Valid Address for reading Toggle Bits (DQ2, DQ6) status data (see Write Operation Status section). 2. Illustration shows first two status read cycles after command sequence, last status read cycle and array data read cycle.
Figure 20. Toggle Polling Timings (During Automatic Algorithms)
30
Rev. 1.0/Jan. 02
HY29F400A
AC CHARACTERISTICS
Enter Automatic Erase Erase Suspend Erase Erase Suspend Read Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete
WE#
DQ[6] DQ[2]
Notes: 1. The system may use CE# or OE# to toggle DQ[2] and DQ[6]. DQ[2] toggles only when read at an address within an erase-suspended sector.
Figure 21. DQ[2] and DQ[6] Operation Sector Protect and Unprotect, Temporary Sector Unprotect
Parameter JE D E C Std tST tRSP tCE tOE tVIDR tVLHT tWPP1 tWPP2 tOESP tCSP Description Voltage Setup Time RESET# Setup Time for Temporary Sector Unprotect Chip Enable to Output Delay Output Enable to Output Delay VID Transition Time for Temporary Sector Unprotect 1 VID Transition Time for Sector Protect and Unprotect 1 Write Pulse Width for Sector Protect Write Pulse Width for Sector Unprotect OE# Setup Time to WE# Active 1 CE# Setup Time to WE# Active 1 Min Min Max Max Min Min Min Min Min Min 50 25 55 25 Speed Option - 50 - 55 4 4 70 30 500 500 100 100 4 4 90 35 - 70 - 90 Unit s s ns ns ns ns s ms s s
Notes: 1. Not 100% tested.
V ID
RESET#
0 or 5V 0 or 5V
tVIDR
tVIDR
CE#
WE# tRSP RY/BY#
Figure 22. Temporary Sector Unprotect Timings
Rev. 1.0/Jan. 02
31
HY29F400A
AC CHARACTERISTICS
Sector Protect Cycle A[17:12] A[0] A[1] A[6] t VID VLHT A[9] tST
VID
Protect Verify Cycle SAX SAY
tVLHT
tVLHT
OE# tVLHT WE# tOE CE# Data RESET# tST VCC 0x01 tOESP tWPP1 tST
tST
Figure 23. Sector Protect Timings
32
Rev. 1.0/Jan. 02
HY29F400A
AC CHARACTERISTICS
Sector Unprotect Cycle
Unprotect Verify Cycle
A[17:12] A[0] A[1] A[6]
VID
SA0
SA1
A[9] tVLHT
VID
tST
tVLHT
tST
OE# tOESP
VID
tOE
CE# tCSP WE# Data RESET# VCC 0x00 tWPP2 tCE
tST
Figure 24. Sector Unprotect Timings
Rev. 1.0/Jan. 02
33
HY29F400A
AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations
Parameter JE D E C tAVAV tAVEL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL Std tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH Description Write Cycle Time 1 Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Byte Mode tWHWH1 tWHWH1 Programming Operation 1, 2, 3 Word Mode Byte Mode Chip Programming Operation 1, 2, 3, 5 Word Mode Min Min Min Min Min Min Min Min Min Min Typ Max Typ Max Typ Max Typ Max Typ Max Typ Max Typ Min Min Speed Option - 50 - 55 50 45 25 55 0 45 25 0 0 0 0 30 30 35 45 20 7 300 12 500 3.6 10.8 3.13 9.3 1 8 11 88 1,000,000 100,000 30 30 45 30 45 45 - 70 70 - 90 90 Unit ns ns ns ns ns ns ns ns ns ns s s s s se c se c se c se c se c se c se c se c cycles cycles ns
tWHWH2 tWHWH3
tWHWH2 Sector Erase Operation 1, 2, 4 tWHWH3 Chip Erase Operation 1, 2, 4 Erase and Program Cycle Endurance tBUSY CE# to RY/BY# Delay
30
35
Notes: 1. Not 100% tested. 2. Typical program and erase times assume the following conditions: 25 C, VCC = 5.0 volts, 100,000 cycles. In addition, programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case conditions of 90 C, VCC = 4.5 volts (4.75 volts for 55 ns version), 100,000 cycles. 3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program command. See Table 5 for further information on command sequences. 4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes are programmed to 0x00 before erasure. 5. The typical chip programming time is considerably less than the maximum chip programming time listed since most bytes program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum byte program time specified is exceeded. See Write Operation Status section for additional information.
34
Rev. 1.0/Jan. 02
HY29F400A
AC CHARACTERISTICS
0x555 for Program 0x2AA for Erase
PA for Program SA for Sector Erase 0x555 for Chip Erase
Addresses tWC WE# tGHEL OE# tWS CE# tDS Data
0xA0 for Program 0x55 for Erase PD for Program 0x30 for Sector Erase 0x10 for Chip Erase
VA tAS tAH
tWH tCP tCPH tWHWH1 or tWHWH2 or tWHWH3 tBUSY Status DOUT
tDH
RY/BY# tRH RESET#
Notes: 1. PA = program address, PD = program data, VA = Valid Address for reading program or erase status (see Write Operation Status section), DOUT = array data read at VA. 2. 3. 4. Illustration shows the last two cycles of the program or erase command sequence and the last status read cycle. Word mode addressing shown. RESET# shown only to illustrate tRH measurement references. It cannot occur as shown during a valid command sequence.
Figure 25. Alternate CE# Controlled Write Operation Timings
Rev. 1.0/Jan. 02
35
HY29F400A
Latchup Characteristics
Description Input voltage with respect to VSS on all pins except I/O pins (including A[9], OE# and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Minimum -1.0 - 1.0 - 100 Maximum 12.5 VCC + 1.0 100 Unit V V mA
Notes: 1. Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at a time.
TSOP and PSOP Pin Capacitance
Sy mb o l CIN COUT CIN2 Par amet er Input Capacitance Output Capacitance Control Pin Capacitance Tes t Set u p VIN = 0 VOUT = 0 VIN = 0 Ty p 6 8.5 7.5 Max 7.5 12 9 Un it pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions: TA = 25 C, f = 1.0 MHz.
Data Retention
Par amet er Minimum Pattern Data Retention Time Tes t Co n d it io n s 150 C 125 C Mi n i mu m 10 20 Un it Years Years
36
Rev. 1.0/Jan. 02
HY29F400A
PACKAGE DRAWINGS Physical Dimensions TSOP48 - 48-pin Thin Small Outline Package (measurements in millimeters)
0.95 1.05 Pin 1 ID
1 48
11.90 12.10
0.50 BSC
24
25
18.30 18.50 19.80 20.20
0.05 0.15
1.20 MAX 0.25MM (0.0098") BSC 0 o 5 0.50 0.70
o
0.08 0.20 0.10 0.21
PSOP44 - 44-pin Plastic Small Outline Package (measurements in millimeters)
44 23
15.70 16.30 13.10 13.50
O O
0.10 0.21 0 8 0.60 1.00
1 1.27 NOM. 28.00 28.40 2.17 2.45
22
2.80 MAX. SEATING PLANE 0.35 0.50 0.10 0.35
Rev. 1.0/Jan. 02
37
HY29F400A
ORDERING INFORMATION Hynix products are available in several speeds, packages and operating temperature ranges. The ordering part number is formed by combining a number of fields, as indicated below. Refer to the `Valid Combinations' table, which lists the configurations that are planned to be supported in volume. Please contact your local Hynix representative or distributor to confirm current availability of specific configurations and to determine if additional configurations have been released.
HY29F400A X X X X X SPECIAL INSTRUCTIONS TEMPERATURE RANGE Blank = Commercial ( 0 to +70 C) I = Industrial (-40 to +85 C) SPEED OPTION 50 55 70 90 PACKAGE TYPE G = 44-Pin Plastic Small Outline Package (PSOP) T = 48-Pin Thin Small Outline Package (TSOP) R = 48-Pin Thin Small Outline Package (TSOP) with Reverse Pinout BOOT BLOCK LOCATION T = Top Boot Block Option B = Bottom Boot Block Option DEVICE NUMBER HY29F400A = 4 Megabit (512K x 8/256K x 16) CMOS 5 Volt-Only Sector Erase Flash Memory = = = = 50 55 70 90 ns ns ns ns
VALID COMBINATIONS 1
P ackag e an d S p eed PSOP Temperature Commercial Industrial G-50 G-55 G-70 G-50I G-55I G-70I G-90 G-90I T-50 T-50I TSOP T-55 T-55I T-70 T-70I T-90 T-90I Reverse TSOP R-50 R-55 R-70 R-50I R-55I R-70I R-90 R-90I 50 n s 55 n s 70 n s 90 n s 50 n s 55 n s 70 n s 90 n s 50 n s 55 n s 70 n s 90 n s
Note: 1. The complete part number is formed by appending the Boot Block Location code and the suffix shown in the table above to the Device Number. For example, the part number for a 90 ns, Commercial temperature range device in the reverse TSOP package with the top boot block option is HY29F400ATR-90.
38
Rev. 1.0/Jan. 02
HY29F400A Important Notice
(c) 2002 by Hynix Semiconductor America. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Hynix Semiconductor Inc. or Hynix Semiconductor America (collectively "Hynix"). The information in this document is subject to change without notice. Hynix shall not be responsible for any errors that may appear in this document and makes no commitment to update or keep current the information contained in this document. Hynix advises its customers to obtain the latest version of the device specification to verify, before placing orders, that the information being relied upon by the customer is current. Devices sold by Hynix are covered by warranty and patent indemnification provisions appearing in Hynix Terms and Conditions of Sale only. Hynix makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Hynix makes no warranty of merchantability or fitness for any purpose. Hynix's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Hynix prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustain life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
Rev. 1.0/Jan. 02
39
HY29F400A
R evision R ecord R ev.
1.0 1.1
D ate
1/02 1/29 Ini ti al release.
D etails
C hange Access speed from 45, 55, 70, 90ns to 50, 55, 70, 90ns
Flash Memory Business Unit, Korea Hynix Semiconductor Inc. 891, Daechi-dong Kangnam-gu Seoul, Korea Telephone: +82-2-3459-5980 Fax: +82-2-3459-5988 http://www.hynix.com
40
Flash Memory Business Unit HQ Hynix Semiconductor Inc. 3101 North First Street San Jose, CA 95134 USA Telephone: (408) 232-8800 Fax: (408) 232-8805 http://www.us.hynix.com
Rev. 1.0/Jan. 02

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